Substrates for iii-nitride epitaxy

ABSTRACT

A wafer suitable for epitaxial growth of gallium nitride (GaN) in a Metal Oxide Chemical Vapor Deposition (MOCVD) process. The wafer includes a silicon substrate having a front side and a back side and an edge extending between the front side and the back side, the edge including a front bevel surface connected to the front side and a back bevel surface connected to the back side, wherein the silicon substrate comprises an oxygen denuded silicon layer surrounding a core. The wafer further includes a protection layer being a thermally grown silicon oxide (SiO 2 ) layer substantially covering the front bevel surface and the back bevel surface of the edge, while leaving at least a central region of the front side of the silicon substrate exposed, for preventing meltback during the MOCVD process.

This application claims priority to UK Patent Application No. 1810251.7filed on Jun. 22, 2018, the entire contents of which are herebyincorporated by reference.

TECHNICAL FIELD

The disclosure relates to substrates for group-III nitride epitaxy andprocesses for preparing such substrates.

BACKGROUND

Group-III nitride semiconductors, such as gallium nitride, have arelatively wide band gap and are used to make light emitting diodes(LEDs) and power devices. The semiconductors can be manufactured byepitaxial growth on a silicon substrate, for example in a Metal OxideChemical Vapor Deposition (MOCVD) process.

The typical temperature of a group-III nitride MOCVD process is in therange of 1000° C. to 1200° C. At such high temperatures the reactionbetween Si and Ga becomes very strong and causes so called “Melt BackEtching” (MBE), which is a known problem for GaN on Si technology. Thepresence of MBE defects can significantly limit the epitaxy (EPI)process yield and the EPI process window. To avoid this issue, a Ga freeprotection layer, such as aluminium nitride (AlN), can be depositedduring epitaxy before starting the GaN growth. However, the area nearthe substrate bevel (i.e. the edge of the substrate) and the bevelledregion itself cannot be completely protected, and MBE will usually occurthere. The Si crystal orientation at the bevel is different to that ofthe flat substrate surface, which prevents continuous growth of AlN andresults in access of Si by Ga during epitaxy. Another mechanism causingMBE is the formation of small cracks in the EPI layer during growth,which provides openings to the Si.

EP 2 945 185 A1 describes the use of an edge-mask layer to cover thebevel. Two processes for making this edge-mask layer are described. Oneis a lift off process of the deposited edge-mask layer, to keep it onlynear the wafer bevel. The other is a direct etch at the centre toachieve the same result. Both processes require one to one exposecapability, which may not be available for big diameter substrates andmay increase the manufacturing cost.

U.S. Pat. No. 9,006,865 describes roughening the substrate at the waferedge, to prevent the EPI layers from cracking during epitaxy. Theroughened substrate surface stimulates polycrystalline growth ofgroup-III nitrides, and hence releases mismatch stress which is the rootcause of the cracking.

U.S. Patent Application Publication No. 2015/0017790 describes the useof an asymmetrical bevel shape. The shape provides a reduced area of thebevel with different crystal orientation, which gives better AlNcoverage. This approach requires custom processing of the substrate atthe substrate vendor or another external service, which may increasemanufacturing costs.

SUMMARY

Aspects of the present invention provide wafers suitable for epitaxialgrowth of a group-III nitride semiconductor and methods of preparingsuch wafers as set out in the accompanying claims.

Certain embodiments of the invention are described below, by way ofexample only, with reference to the accompanying drawings.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1a is a top view of a Si wafer according to an embodiment;

FIG. 1b is a side cross-sectional view of a Si wafer according to theembodiment;

FIG. 2 is a side cross-sectional view of a portion of a wafer accordingto an embodiment;

FIG. 3 is a diagram showing temperature plotted against time for a waferpreparation process according to an embodiment;

FIG. 4 is a series of schematic diagrams illustrating processes of waferpreparation according to embodiments;

FIG. 5 is a series of schematic diagrams illustrating a process of waferpreparation according to another embodiment; and

FIG. 6 is a flow diagram illustrating the steps of a method of preparinga wafer according to an embodiment.

DETAILED DESCRIPTION

The disclosed embodiments relate to substrate preparation prior togroup-III nitride (e.g. AlN, InN or GaN or their alloy (AlGaN or InGaNfor example)) on silicon (Si) epitaxy. The embodiments may solve atleast some of the above mentioned issues of the prior solutions to MeltBack Etching (MBE), and may solve further, previously unanticipated,problems. The embodiments can provide substrate bevel protection inorder to suppress MBE during group-III nitride MOCVD processes. Thesubstrate bevel protection can significantly improve EPI wafer yield andthe size of the EPI process window.

FIGS. 1a and 1b illustrate a wafer 2 suitable for epitaxial growth ofGaN according to an embodiment. FIG. 1a is a top view of the wafer 2comprising a silicon substrate 4 and a protection layer 6 (e.g. an oxidelayer). The protection layer 6 covers the edge 8 of the substrate 4,such that only a central region 10 of the front side 12 of the substrate4 is exposed. FIG. 1b is a side cross-sectional view of the wafer 2. Theoxide layer 6 covers the edge 8 and the back side 14 of the wafer. Thesilicon substrate 4 comprises a core 16 and a surrounding oxygen denudedsilicon layer 18 (also referred to simply as “denuded layer” 18). Theprotection layer 6 does not cover the central region 10 of the frontside 12, such that the denuded layer 18 in this region 10 is exposed. Agroup-III nitride semiconductor can be grown on the denuded siliconlayer 18 in the central region 10. For example, a buffer layercomprising AlN can be grown in the central region 10 followed by GaN.

The buffer layer can be a layer comprising one of aluminium nitride,AlN, indium nitride, InN, aluminium gallium nitride, AlGaN, indiumaluminium nitride, InAlN, and indium aluminium gallium nitride, InAlGaN,or can be formed from a stack of layers formed from any combination ofthese materials.

A drawback of some prior solutions is that they do not cover the backside of the bevelled edge or the back side of the substrate. This meansthat formation of MBE is still possible at the back side of the bevel,where Ga can reach Si for some growth conditions. Also, by notprotecting the back side of the substrate, it can be contaminated by theplatter (i.e. the wafer holder inside of EPI reactor) leading to futurecross contamination risk. The embodiment illustrated in FIGS. 1a and 1bsolves this problem by providing a protection layer 6, which covers thewhole edge 8 (i.e. front and back of the bevelled edge 8) and the backside 14 of the substrate.

FIG. 2 shows an edge portion 20 of the wafer 2 according to anembodiment. The edge 8 of the substrate 4 comprises a front bevelsurface 22 connected to the front side 12 of the substrate 4, and a backbevel surface 24 connected to the back side 14 of the substrate 4. Theprotection layer 6 (e.g. an oxide layer) covers the whole edge 8,including the front bevel surface 22 and the back bevel surface 24. Thefront bevel surface 22 is defined herein as the surface of the siliconsubstrate 4 extending from the curve 23 (adjacent the front side 12 ofthe substrate 4 where the substrate starts to curve/angle downwards) tothe outermost edge 9. The back bevel surface is similarly defined hereinas the surface extending from the curve 25 (adjacent the back side 14 ofthe substrate 4 where the substrate starts to curve/angle upwards) tothe outermost edge 9. Accordingly, if the edge 8 is symmetrical, thefront bevel surface 22 meets the back bevel surface 24 along themid-plane 27 of the substrate 4. The protection layer 6 extends a smalldistance from the edge 8 onto the front side 12 of the substrate 4, suchthat only a central region 10 of the front side 12 is exposed. Also theback side 14 of the substrate 4 is covered by the protection layer 6,such that only the central region 10 on the front side 12 of thesubstrate 4 is exposed. The protection layer 6 has a thickness 26, whichmay vary along the edge 8. The protection layer 6 may have a thicknessgreater than 100 nm, for example in the range of 100 nm to 1000 nm, andmore specifically in one case in the range of 200 nm to 600 nm. Theprotection layer 6 can have a thickness smaller than the thickness ofthe EPI layer (e.g. the GaN layer) to be grown.

An additional disadvantage of a prior system (see e.g. U.S. PatentApplication Publication No. 2015/0017790) is that the oxide thicknesshas to be greater than the group-III nitride thickness (for reasons notstated in U.S. 2015/0017790), which can make the thermal oxidizationprocess too long leading to a high risk of degradation of the mechanicalproperties of the substrate. In the prior system, the protective layerat the bevel then has to be removed after the EPI process (for reasonsnot stated in U.S. 2015/0017790) which requires additional processsteps. Embodiments described herein can have a thinner oxide layer as aresult of the improved substrate preparation process, which does notrequire additional process steps to remove the protective layer afterthe EPI process.

Another aspect which has to be considered is substrate annealing andother thermal treatments at the beginning of the GaN on Si EPI process.To start the epitaxy growth processes, the native SiO₂ has to beremoved. Historically, a wet process was adopted for this purpose, butnowadays in-situ pre-EPI substrate annealing in a hydrogen-containingatmosphere is more common. The pre-EPI substrate annealing has theadvantage of reduced wafer handling, better particle contaminationcontrol, and there is no need for wet equipment. A drawback of thisapproach is that the in-situ annealing process has a relatively narrowprocess window, and it is very sensitive to the EPI reactorprecondition. The reason is that native SiO₂ annealing typically occursat 1000° C. to 1100° C., where oxygen precipitation formation in the Sisubstrate is very efficient. The precipitation centres attractcontamination from the duty EPI reactor environment and cansignificantly damage substrate surface quality. Degradation of thesubstrate quality leads to an increase of the crystal micro and macrodefects in the grown group-III nitride or even MBE formation if themacro defects are big enough to support Ga access to the Si. Thedescribed pre-EPI substrate preparation provides the oxygen denuded Silayer near the substrate surface, which creates an oxygen precipitationfree surface during the initial thermal treatment steps of the GaN on SiEPI process and can hence make the overall EPI process more stable.Uncontrolled oxygen precipitation in the depth of the Si substrateduring EPI growth (which is 6 to 8 hours or longer at a temperature ofabout 1100° C.) may lead to a significant change in the mechanicalproperties of the Si substrate and lead to strain management failure.

The substrate preparation process according to an embodiment can bedivided into three main stages as illustrated in FIG. 3. FIG. 3 shows atemperature profile used to provide “intrinsic gettering” in thesilicon. Gettering is a process in which contaminants are moved awayfrom the surface of a semiconductor and into the bulk (core) where theyare trapped, thereby creating a denuded zone at the surface.

The first step (T1, Out-diffusion): The first oxidation and subsequentannealing. The first oxidation is performed in an oxygen containingatmosphere at temperature of about 1000° C. to achieve an oxide layerthickness of about 10 nm to 60 nm. The purpose of this oxide layer b1 isto generate an oxygen denuded Si layer a101 and to protect the Sisurface during further process steps. During oxidation in a diluted orpure oxygen atmosphere, an intrinsic interstitial oxide (Oi) in silicondiffuses to the surface and a denuded zone a101 (i.e. the oxygen denudedsilicon layer) is formed. Depending on the oxidation and annealing time,the denuded zone a101 may be between 10 μm and 30 μm thick, or between 5μm and 50 μm thick. The target thickness and the oxidation conditionsare selected so as to avoid precipitation formation inside the denudedzone a101, and so that only very small nucleation seeds in the substratecore al (under the denuded zone) are possible. It is necessary to createa denuded layer a101 and enough oxide thickness to provide sufficient Sisurface protection. Subsequent annealing is performed in an oxygen freeatmosphere (for example in N or Ar) to improve the SiO₂/Si interfacequality and to cause further O₂ out-diffusion.

The second step (T2, Nucleation): Formation of the precipitation seeds.During this step precipitation seeds a102 are formed in the core of theSi substrate (but not in the denuded silicon layer). The core may have aprecipitation size of 2 nm to 20 nm, for example. This step can beperformed specifically for the purpose of nucleation (e.g. with aramp-down phase from 1000° C. to between 600° C. and 800° C., and afollowing cool down phase at this temperature), or it can be a sideeffect of another required treatment, for example Low Pressure ChemicalVapor Deposition (LPCVD) silicon nitride (SiN) hard mask deposition. ForLPCVD SiN deposition a temperature lower than the oxidation temperatureis used (e.g. between 650° C. and 800° C. for more than 30 min).

The third step (T3, Precipitation a103 growth): The second (main)oxidation. The oxide grown in this step (e.g. oxide layer 6 in FIGS. 1a,1b and 2) provides protection for the substrate bevel. The thickness ofthis oxide should be about 100 nm to 500 nm. The lower limit (about 100nm) is set such that there is sufficient thickness to continuously coverthe wafer bevel throughout the remaining EPI process steps. The upperlimit (about 500 nm) depends on the thermal budget and process timelimit. The oxidation conditions (time, temperature, atmosphere andannealing after oxidation) can be selected according to substrate type(e.g. in terms of doping, oxygen content, crystal orientation andepitaxy temperature) in order to have proper precipitation (greater thanabout 2 nm to 5 nm, to be stable up to 1100° C. epitaxy). If themechanical properties of the substrate are required to remain unchanged,the precipitation size should be small enough to tend to dissolve at thegroup-III nitride EPI growth temperature. If there is a need to make thesubstrate less brittle, a bigger size of precipitation a103 can be used.Uncontrolled precipitation growth can lead to significant change of thesubstrate's mechanical properties and loss of the wafer strainmanagement control.

FIG. 4 illustrates different processes for making a wafer using apositive resist according to an embodiment. FIG. 4 is divided intoseparate steps labelled ‘a’ to ‘i3’, and each step is described below.To aid understanding, features of the wafer in FIG. 4 similar to thosein FIGS. 1a and 1b have been given the same reference numerals, but thewafer produced by a process illustrated in FIG. 4 is not limited to thewafer of FIGS. 1a and 1 b.

a. The process starts with a bare silicon substrate 4.b. A first oxidation and annealing is performed to form a first oxidelayer 30 and to generate a denuded layer 18 around a core 16 of thesilicon substrate 4. The first oxide layer 30 is relatively thin and hasa thickness in the range of 10 nm to 60 nm. The oxide growth is followedby annealing in the oxygen free atmosphere at a similar temperaturecausing the denuded zone 18 to grow further.c. A thin (about 10 nm to 100 nm) silicon nitride (SiN) layer 32 isdeposited. The SiN layer 32 will be used as a hard mask at a laterstage.d. The wafer is coated with resist 34. After resist coating the wafer,edge light exposure is performed directly in the resist coating tool.This allows the process to be carried out without the need for a steppertool (which is generally expensive). The resist 34 is developed toexpose the underlying SiN layer 32 around the edge of the substrate 4.e1 to e6. After the resist development, a SiN etch is performed to forma SiN hard mask 32. Each step of e1 to e6 illustrates a different resultof performing the SiN etch, wherein the difference depends on theavailable equipment and other requirements. In all cases, the centralregion on the front side of the substrate stays covered by the SiN hardmask 32.e1 and e4. When the selected etch conditions are close to perfectlyisotropic, the SiN 32 (or SiN 32 and oxide layer 30) will be etched atthe back side of the bevel and even on the back side of the substrate 4.e3 and e6. In the case where anisotropic etching dominates, the SiN 32(or SiN 32 and oxide layer 30) will only be etched on the front side ofthe wafer and bevel. The back side of the wafer is still covered by SiN.e2 and e5. In an intermediate case, the SiN 32 (or SiN 32 and oxidelayer 30) are etched on the front side and the back side of the beveledge but not on the back side of the substrate 4.g1 to g3. The resist 34 is stripped away. After the resist strip, asecond oxidation is performed to form a second oxide layer 6 (which willbecome the protection later). Depending on the process requirements,this second oxide thickness may vary from 150 nm to 600 nm, but needs tobe at least thick enough to provide sufficient bevel protection. Whendesigning the second oxide thickness, the consumption of oxide 6 at thebevel during the subsequent steps of SiN hard mask removal and oxideetching has to be considered. Due to the presence of the SiN hard mask32, the oxide 6 will only grow in the area where SiN was previouslyremoved. Also, precipitation growth, out of denuded layer 18, occurs inthe silicon substrate core 16. For clarity, step g1 follows from eithere1 or e4, step g2 follows from either e2 or e5, and step g3 follows fromeither e3 or e6.h1 to h3. After the second oxidation, the SiN hard mask 32 is removed.This will generally also reduce the thickness of the oxide layer 6 by asmall amount. Group-III nitride epitaxy processes are very sensitive tothe Si surface quality, and the SiN etch has to be stopped at the firstoxide 30 to avoid Si damage.i1 to i3. The oxide layer 30 in the central region 10 of the substrate 4is removed. For example, a diluted HF (hydrofluoric acid) or buffered HF(BOE) oxide etch step is carried out to completely remove the underlyingthin oxide layer 30.

FIG. 5 shows an alternative embodiment, in which a negative resist isused. The use of a negative resist removes the need for a SiN hard mask.FIG. 5 is divided into 5 steps, labelled ‘a’ to ‘e’, illustrating theprocess.

a. A bare Si substrate 4 is provided.b. First oxidation to form first oxide layer 30 is performed. Annealinggenerates a denuded Si layer 18 around the core 16, and in-situ seedformation in the core 16 after ramp-down to between 650° C. and 800° C.under N₂. The time for seed formation is typically 2 to 4 hours.c. After ramp-up to between 900° C. and 950° C., the protection oxidegrowth is in-situ in the range of 100 nm to 500 nm under wet atmosphere.The following in-situ annealing (between 0.5 and 4 hours) under a N₂ orAr atmosphere depends on the necessary precipitate diameter to be stableduring epitaxy ramp-up to 1100° C. and 1st epitaxy layer growth.d. The lithography step (similar to one used for positive resist asillustrated in FIG. 4) is performed to coat the oxide layer 6 at theedge 8 with resist 36.e. An oxide etch at the central region 10 of the substrate 4 isperformed, followed by resist removal and cleaning to complete theprocess.

FIG. 6 is a flow diagram illustrating the steps of a method of preparinga wafer according to an embodiment. The method may be used with eitherpositive or negative resist. To aid understanding, reference numeralsgiven in the method below refer back to the edge portion of a wafershown in FIG. 2, but the method is not limited to the wafer of FIG. 2.The method comprises providing a silicon substrate 4 having a front side12 and a back side 14 and an edge 8 extending between said front side 12and said back side 14, said edge 8 comprising a front bevel surface 22connected to said front side 12 and a back bevel surface 24 connected tosaid back side 14 (step S1), annealing said substrate 4 to form anoxygen denuded silicon layer 18 surrounding a core 16 in said substrate4 (step S2), and forming a protection layer 6 covering said front bevelsurface 22 and said back bevel surface 24 of said edge 8, while leavingat least a central region 10 of said front side 12 of said siliconsubstrate 4 exposed (step S3).

The step S2 of annealing the substrate may be a first of several stepsof annealing during the wafer preparation. The step may compriseannealing at a temperature of 1000° C. for a period of time such thatsaid oxygen denuded silicon layer has a thickness in the range of 10 μmto 30 μm, or in the range 5 μm to 50 μm. After annealing the substrate 4(step S2), the temperature may be reduced (ramp-down) to between 600° C.and 800° C. to form precipitation seeds in the core of the substrate.

If a positive resist is used, step S3 of the illustrated method maycomprise performing a first oxidation to form a first oxide layer (e.g.10 nm to 60 nm thick), forming a silicon nitride, SiN, hard mask on saidfirst oxide layer, wherein said hard mask covers said central region anddoes not cover said front bevel surface, performing a second oxidationto form a second oxide layer (e.g. 100 nm to 600 nm thick) being saidprotection layer, wherein said second oxide layer is grown on thesubstrate in regions not covered by said hard mask, removing said hardmask from said first oxide layer in said central region, and performingan oxide etch to remove said first oxide layer from said central region.The step of forming said SiN hard mask may comprise, depositing a SiNlayer on said first oxide layer, coating said SiN layer with a resist,developing said resist, and performing a SiN etch to remove said SiNlayer from an area not covered by said resist.

If a negative resist is used, step S3 of the illustrated method maycomprise providing an oxide layer (e.g. 100 nm to 600 nm thick) coveringsaid substrate, coating said oxide layer with a resist, developing saidresist, and performing an oxide etch to remove said oxide layer fromsaid substrate in an area not covered by said resist to expose saidcentral region. Using a negative resist requires only one oxidation stepand no SiN hard mask. However, negative resist is not always available.

Some advantages of the described embodiments include:

-   -   Improved bevel protection using processes available in the        standard CMOS foundry environment.    -   The process can be applied to any kind of Si wafer (regardless        of thickness, doping, diameter, etc.)    -   The process does not require any mask and lithography stepper        tool.    -   All bevel surfaces (back and front bevel surfaces) and the Si        wafer back surface is protected.    -   The EPI ready Si surface is formed with an oxygen denuded Si        layer (up to between 10 μm and 20 μm depth), which provides        better substrate surface quality control during the initial GaN        on Si EPI steps.    -   The mechanical properties of the wafer remain substantially        unchanged after the process.

While specific embodiments of the invention have been described above,it will be appreciated that the invention as defined by the claims maybe practiced otherwise than as described. The descriptions above areintended to be illustrative, not limiting. It will be apparent to oneskilled in the art that modifications may be made to the invention asdescribed without departing from the scope of the claims set out below.

Each feature disclosed or illustrated in the present specification maybe incorporated in the invention, whether alone or in any appropriatecombination with any other feature disclosed or illustrated herein.

What is claimed is:
 1. A wafer suitable for epitaxial growth of galliumnitride (GaN) in a Metal Oxide Chemical Vapor Deposition (MOCVD)process, said wafer comprising: a silicon substrate having a front sideand a back side and an edge extending between said front side and saidback side, said edge comprising a front bevel surface connected to saidfront side and a back bevel surface connected to said back side, whereinsaid silicon substrate comprises an oxygen denuded silicon layersurrounding a core; and a protection layer being a thermally grownsilicon oxide (SiO₂) layer substantially covering said front bevelsurface and said back bevel surface of said edge, while leaving at leasta central region of said front side of said silicon substrate exposed,for preventing meltback during said MOCVD process.
 2. A wafer accordingto claim 1, wherein said protection layer also covers said back side ofsaid silicon substrate, such that only said central region is exposed.3. A wafer according to claim 1, further comprising a group-III nitridelayer covering said central region.
 4. A wafer according to claim 3,wherein said group-III nitride layer comprises one of aluminium nitride,AlN, indium nitride, InN, gallium nitride, GaN, aluminium galliumnitride, AlGaN, indium aluminium nitride, InAlN, and indium aluminiumgallium nitride, InAlGaN, or is formed from a stack of layers formedfrom any combination of these materials.
 5. A wafer according to claim1, wherein said protection layer has a thickness greater than 100 nm, orin the range of 100 nm to 1000 nm, or in the range of 200 nm to 600 nm.6. A wafer according to claim 1, wherein said oxygen denuded siliconlayer has a thickness in the range of 5 μm to 50 μm.
 7. A waferaccording to claim 1, wherein said core has a precipitation size in therange of 2 nm to 20 nm.
 8. A wafer according to claim 1, furthercomprising a silicon nitride, SiN, layer covering said back side of saidsilicon substrate.
 9. A wafer according to claim 1, wherein said SiNlayer covers said back bevel surface.
 10. A method of preparing a wafersuitable for epitaxial growth of gallium nitride in a Metal OxideChemical Vapor Deposition (MOCVD) process, said method comprising:providing a silicon substrate having a front side and a back side and anedge extending between said front side and said back side, said edgecomprising a front bevel surface connected to said front side and a backbevel surface connected to said back side; forming a protection layerbeing a thermally grown silicon oxide (SiO₂) layer covering said frontbevel surface and said back bevel surface of said edge, while leaving atleast a central region of said front side of said silicon substrateexposed; and forming an oxygen denuded silicon layer surrounding a corein said substrate.
 11. A method according to claim 10, wherein said stepof forming said protection layer comprises forming said protection layersuch that it also covers said back side of said silicon substrate.
 12. Amethod according to claim 10, wherein said step of forming saidprotection layer comprises: performing a first oxidation of said siliconsubstrate to form a first oxide layer; forming a silicon nitride, SiN,hard mask on said first oxide layer, wherein said hard mask covers saidcentral region and does not cover said front bevel surface; performing asecond oxidation of said silicon substrate to form a second oxide layerbeing said protection layer, wherein said second oxide layer is grown onthe substrate in regions not covered by said hard mask; removing saidhard mask from said first oxide layer in said central region; andperforming an oxide etch to remove said first oxide layer from saidcentral region.
 13. A method according to claim 12, wherein said step offorming said SiN hard mask comprises: depositing a SiN layer on saidfirst oxide layer; coating said SiN layer with a resist; developing saidresist; and performing a SiN etch to remove said SiN layer from an areanot covered by said resist.
 14. A method according to claim 12, whereinsaid step of performing said second oxidation comprises growing saidsecond oxide layer to have a thickness in the range of 100 nm to 1000nm.
 15. A method according to claim 12, wherein said step of removingsaid SiN hard mask comprises performing a SiN etch down to said firstoxide layer.
 16. A method according to claim 12, wherein said step ofperforming an oxide etch comprises a diluted hydrofluoric acid, HF, orbuffered HF oxide etch step.
 17. A method according to claim 10, whereinsaid step of forming said protection layer comprises: providing an oxidelayer covering said substrate; coating said oxide layer with a resist;developing said resist; and performing an oxide etch to remove saidoxide layer from said substrate in an area not covered by said resist toexpose said central region.
 18. A method according to claim 10, whereinsaid method is performed in a standard Complementary Metal OxideSemiconductor, CMOS, process.
 19. A method according to claim 10,further comprising annealing said substrate to grow said oxygen denudedsilicon layer.
 20. A method according to claim 19, wherein said step ofannealing comprises annealing at a temperature of 800 to 1,200° C. for aperiod of time such that said oxygen denuded silicon layer has athickness in the range of 10 μm to 30 μm.
 21. A method according toclaim 19, further comprising, after said step of annealing, reducing atemperature to between 600° C. and 800° C. to form precipitation seedsin said core of said substrate.
 22. A method according to claim 10 usedto prepare a wafer as claimed in claim 1.